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Design & implementation of digital components using Rev. Logic Gates - Softcover

 
9786139458967: Design & implementation of digital components using Rev. Logic Gates

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Implementing the already existing circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing, etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication …etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis is to minimize the garbage, to minimize the delay, to minimize the total number of gates and also to minimize the width of the circuit. In this paper, designer implemented 2:1 MUX, D-Flip-Flop, Vedic multiplier and PIPO shift register using reversible logic gates.

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  • PublisherLAP LAMBERT Academic Publishing
  • Publication date2019
  • ISBN 10 613945896X
  • ISBN 13 9786139458967
  • BindingPaperback
  • LanguageEnglish
  • Number of pages52

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J. N., Ravi; S., Madan
Published by LAP LAMBERT Academic Publishing, 2019
ISBN 10: 613945896X ISBN 13: 9786139458967
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Ravi J. N., Madan S.
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J. N., Ravi; S., Madan
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Implementing the already existing circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing, etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication .etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis is to minimize the garbage, to minimize the delay, to minimize the total number of gates and also to minimize the width of the circuit. In this paper, designer implemented 2:1 MUX, D-Flip-Flop, Vedic multiplier and PIPO shift register using reversible logic gates. 52 pp. Englisch. Seller Inventory # 9786139458967

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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Implementing the already existing circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing, etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication .etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis is to minimize the garbage, to minimize the delay, to minimize the total number of gates and also to minimize the width of the circuit. In this paper, designer implemented 2:1 MUX, D-Flip-Flop, Vedic multiplier and PIPO shift register using reversible logic gates. Seller Inventory # 9786139458967

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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: J. N. RaviRavi J. N., BE: studied ECE in Bangalore Institute of Technology. Currently working in a prestigious VLSI company.Implementing the already existing circuits using reversible logic has drawn a significant interest in rec. Seller Inventory # 281444957

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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Implementing the already existing circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing, etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication ¿etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis is to minimize the garbage, to minimize the delay, to minimize the total number of gates and also to minimize the width of the circuit. In this paper, designer implemented 2:1 MUX, D-Flip-Flop, Vedic multiplier and PIPO shift register using reversible logic gates.Books on Demand GmbH, Überseering 33, 22297 Hamburg 52 pp. Englisch. Seller Inventory # 9786139458967

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