Synopsis
This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.
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Low Power Asynchronous Logic design for Viterbi Decoders
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LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch. Seller Inventory # 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Published by
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Paperback. Condition: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock. Seller Inventory # zk6139851297
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Low Power Asynchronous Logic design for Viterbi Decoders
Published by
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Seller: moluna, Greven, Germany
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and in. Seller Inventory # 385874302
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Low Power Asynchronous Logic design for Viterbi Decoders
Published by
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch. Seller Inventory # 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Published by
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. Seller Inventory # 9786139851294
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