Synopsis
There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach.
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Concept and Design of a High Speed Current Mode Based SAR ADC
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach. 132 pp. Englisch. Seller Inventory # 9786139928019
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Concept and Design of a High Speed Current Mode Based SAR ADC
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Elkafrawy AbdelrahmanDr.-Ing. Elkafrawy received his Ph.D. degree in mixed signal IC design from Institute of Microelectronics, University of Ulm, Germany, in 2016. His field of interests include mixed-mode amplifiers, LDOs, CLK buff. Seller Inventory # 385877710
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Concept and Design of a High Speed Current Mode Based SAR ADC
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ISBN 10: 613992801X
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Concept and Design of a High Speed Current Mode Based SAR ADC
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LAP LAMBERT Academic Publishing Nov 2018, 2018
ISBN 10: 613992801X
ISBN 13: 9786139928019
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 132 pp. Englisch. Seller Inventory # 9786139928019
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Concept and Design of a High Speed Current Mode Based SAR ADC
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Taschenbuch. Condition: Neu. Concept and Design of a High Speed Current Mode Based SAR ADC | Abdelrahman Elkafrawy (u. a.) | Taschenbuch | 132 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139928019 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 115056699
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Concept and Design of a High Speed Current Mode Based SAR ADC
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LAP LAMBERT Academic Publishing, 2018
ISBN 10: 613992801X
ISBN 13: 9786139928019
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach. Seller Inventory # 9786139928019
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Concept and Design of a High Speed Current Mode Based SAR ADC
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