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Performance Analysis of Ternary Multiplier using Booth Encoding: A Novel Approach to Ternary Multiplication - Softcover
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In the world of VLSI, the abundance of battery powered, handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area, the power consumption and the device speed. The high speed data processing, low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems, multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit, 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation, delay and area has been done effectively.
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Performance Analysis of Ternary Multiplier using Booth Encoding
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LAP LAMBERT Academic Publishing Apr 2020, 2020
ISBN 10: 6202520930
ISBN 13: 9786202520935
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the world of VLSI, the abundance of battery powered, handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area, the power consumption and the device speed. The high speed data processing, low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems, multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit, 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation, delay and area has been done effectively. 84 pp. Englisch. Seller Inventory # 9786202520935
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Performance Analysis of Ternary Multiplier using Booth Encoding : A Novel Approach to Ternary Multiplication
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 6202520930
ISBN 13: 9786202520935
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In the world of VLSI, the abundance of battery powered, handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area, the power consumption and the device speed. The high speed data processing, low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems, multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit, 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation, delay and area has been done effectively. Seller Inventory # 9786202520935
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Performance Analysis of Ternary Multiplier using Booth Encoding
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 6202520930
ISBN 13: 9786202520935
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Softcover
Seller: moluna, Greven, Germany
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: KAUR KHUSHDEEPMs. Khushdeep Kaur did her B.E(ECE) and Master of Technology both from Panjab University, Chandigarh, India. She is currently working as an Assistant Professor. Her research interests are VLSI, Microelectronics and Digi. Seller Inventory # 385945855
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Performance Analysis of Ternary Multiplier using Booth Encoding
Published by
LAP LAMBERT Academic Publishing Apr 2020, 2020
ISBN 10: 6202520930
ISBN 13: 9786202520935
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the world of VLSI, the abundance of battery powered, handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area, the power consumption and the device speed. The high speed data processing, low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems, multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit, 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation, delay and area has been done effectively.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 84 pp. Englisch. Seller Inventory # 9786202520935
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Performance Analysis of Ternary Multiplier using Booth Encoding | A Novel Approach to Ternary Multiplication
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 6202520930
ISBN 13: 9786202520935
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Seller: preigu, Osnabrück, Germany
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Taschenbuch. Condition: Neu. Performance Analysis of Ternary Multiplier using Booth Encoding | A Novel Approach to Ternary Multiplication | Khushdeep Kaur | Taschenbuch | 84 S. | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202520935 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 118335718
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