Seller: BargainBookStores, Grand Rapids, MI, U.S.A.
Paperback or Softback. Condition: New. Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis 0.35. Book. Seller Inventory # BBS-9786204720067
Quantity: 5 available
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Condition: New. Seller Inventory # ABLIING23Apr0316110299222
Quantity: Over 20 available
Seller: California Books, Miami, FL, U.S.A.
Condition: New. Seller Inventory # I-9786204720067
Quantity: Over 20 available
Seller: PBShop.store US, Wood Dale, IL, U.S.A.
PAP. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # L0-9786204720067
Quantity: Over 20 available
Seller: PBShop.store UK, Fairford, GLOS, United Kingdom
PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # L0-9786204720067
Quantity: Over 20 available
Seller: Russell Books, Victoria, BC, Canada
paperback. Condition: New. Special order direct from the distributor. Seller Inventory # ING9786204720067
Quantity: Over 20 available
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Condition: New. In. Seller Inventory # ria9786204720067_new
Quantity: Over 20 available
Seller: Chiron Media, Wallingford, United Kingdom
PF. Condition: New. Seller Inventory # 6666-IUK-9786204720067
Quantity: 10 available
Seller: Books Puddle, New York, NY, U.S.A.
Condition: New. Seller Inventory # 26395143349
Quantity: 4 available
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. 100 pp. Englisch. Seller Inventory # 9786204720067
Quantity: 2 available