This book explores the design and optimization of advanced Surrounding Gate Tunnel Field-Effect Transistors (SGTFETs) for future low-power semiconductor technologies. It presents analytical models and TCAD-based investigations of conventional SGTFETs, Triple Material SGTFETs (TMSGTFETs), and III-V High-k SGTFETs, with emphasis on improving switching performance, reducing leakage, and enhancing energy efficiency. The work integrates evolutionary multiobjective optimization using NSGA-III and machine-learning-assisted Pareto Active Learning to identify optimal trade-offs among delay, dynamic power, on-off current ratio, switching speed, and device variability. By combining device physics, computational intelligence, and optimization techniques, the book offers a scalable framework for the development of high-performance nanoscale transistor architectures suitable for next-generation integrated circuits and emerging nanoelectronic applications.
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Paperback. Condition: new. Paperback. This book explores the design and optimization of advanced Surrounding Gate Tunnel Field-Effect Transistors (SGTFETs) for future low-power semiconductor technologies. It presents analytical models and TCAD-based investigations of conventional SGTFETs, Triple Material SGTFETs (TMSGTFETs), and III-V High-k SGTFETs, with emphasis on improving switching performance, reducing leakage, and enhancing energy efficiency. The work integrates evolutionary multiobjective optimization using NSGA-III and machine-learning-assisted Pareto Active Learning to identify optimal trade-offs among delay, dynamic power, on-off current ratio, switching speed, and device variability. By combining device physics, computational intelligence, and optimization techniques, the book offers a scalable framework for the development of high-performance nanoscale transistor architectures suitable for next-generation integrated circuits and emerging nanoelectronic applications. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9786630209815
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Taschenbuch. Condition: Neu. Intelligent Engineering of Advanced Surrounding Gate Tunnel FETs | From Core Device Physics to Machine Learning-Assisted Many-Objective Evolutionary Optimization | Charumathi V (u. a.) | Taschenbuch | Englisch | 2026 | LAP LAMBERT Academic Publishing | EAN 9786630209815 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand. Seller Inventory # 136944795
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book explores the design and optimization of advanced Surrounding Gate Tunnel Field-Effect Transistors (SGTFETs) for future low-power semiconductor technologies. It presents analytical models and TCAD-based investigations of conventional SGTFETs, Triple Material SGTFETs (TMSGTFETs), and III-V High-k SGTFETs, with emphasis on improving switching performance, reducing leakage, and enhancing energy efficiency. The work integrates evolutionary multiobjective optimization using NSGA-III and machine-learning-assisted Pareto Active Learning to identify optimal trade-offs among delay, dynamic power, on-off current ratio, switching speed, and device variability. By combining device physics, computational intelligence, and optimization techniques, the book offers a scalable framework for the development of high-performance nanoscale transistor architectures suitable for next-generation integrated circuits and emerging nanoelectronic applications. 240 pp. Englisch. Seller Inventory # 9786630209815
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Paperback. Condition: new. Paperback. This book explores the design and optimization of advanced Surrounding Gate Tunnel Field-Effect Transistors (SGTFETs) for future low-power semiconductor technologies. It presents analytical models and TCAD-based investigations of conventional SGTFETs, Triple Material SGTFETs (TMSGTFETs), and III-V High-k SGTFETs, with emphasis on improving switching performance, reducing leakage, and enhancing energy efficiency. The work integrates evolutionary multiobjective optimization using NSGA-III and machine-learning-assisted Pareto Active Learning to identify optimal trade-offs among delay, dynamic power, on-off current ratio, switching speed, and device variability. By combining device physics, computational intelligence, and optimization techniques, the book offers a scalable framework for the development of high-performance nanoscale transistor architectures suitable for next-generation integrated circuits and emerging nanoelectronic applications. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. Seller Inventory # 9786630209815
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