Pub Date: 2014-08-01 Pages: 284 Language: Chinese Publisher: Electronic Industry Press book systematically explains the field of communication networks inside Xilinx FPGA IP hard core. To the popular Xilinx Virtex-6 models chip. for example. in the field of communication covering Xilinx FPGA IP core mainstream explain Xilinx FPGA clock resources and DCM. PLL and MMCM clock management features and use; introduce Block RAM resources generated based ROM. RAM. FIFO and CAM use nuclear processes. Elaborated TEMAC nuclear background knowledge. internal structure. interface timing and configuration parameters. given generate instances; introduce LVDS technical specifications. source synchronous implementations and to offset technology. explain Xilinx FPGA in IODELAYE1. ISERDES1 and OSERDES nuclear use; elaborate Xilinx FPGA DDR3 controller IP core structures. module division. the i...
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Seller: liu xing, Nanjing, JS, China
paperback. Condition: New. Pub Date: 2014-08-01 Pages: 284 Language: Chinese Publisher: Electronic Industry Press book systematically explains the field of communication networks inside Xilinx FPGA IP hard core. To the popular Xilinx Virtex-6 models chip. for example. in the field of communication covering Xilinx FPGA IP core mainstream explain Xilinx FPGA clock resources and DCM. PLL and MMCM clock management features and use; introduce Block RAM resources generated based ROM. RAM. FIFO and CAM use nuclear processes. . Seller Inventory # BZ035557
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