In the past two decades, research in VLSI physical design has been directed toward automation of layout process. Since the cost of fabricating a circuit is a fast growing function of the circuit area, circuit layout techniques are developed with an aim to produce layouts with small areas. Other criteria of optimality such as delay and via minimization need to be taken into consideration. This book includes 14 articles that deal with various stages of the VLSI layout problem. It covers topics including partitioning, floorplanning, placement, global routing, detailed routing and layout verification. Some of the chapters are review articles, giving the state-of-the-art of the problems related to timing driven placement, global and detailed routing, and circuit partitioning. The rest of the book contains research articles, giving recent findings of new approaches to the above-mentioned problems. They are all written by leading experts in the field. This book will serve as good references for both researchers and professionals who work in this field.
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Seller: California Books, Miami, FL, U.S.A.
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Seller: moluna, Greven, Germany
Condition: New. KlappentextrnrnDiscussing algorithmic aspects of VLSI layout, this text includes coverage of: issues in timing driven layout LP formulation of global routeing and placement Stockmeyer s floorplan optimization technique the Manhattan and knock. Seller Inventory # 909654594
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Seller: Revaluation Books, Exeter, United Kingdom
Hardcover. Condition: Brand New. 397 pages. 9.00x6.50x1.00 inches. In Stock. Seller Inventory # x-981021488X
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Seller: AHA-BUCH GmbH, Einbeck, Germany
Buch. Condition: Neu. Neuware - In the past two decades, research in VLSI physical design has been directed toward automation of layout process. Since the cost of fabricating a circuit is a fast growing function of the circuit area, circuit layout techniques are developed with an aim to produce layouts with small areas. Other criteria of optimality such as delay and via minimization need to be taken into consideration. This book includes 14 articles that deal with various stages of the VLSI layout problem. It covers topics including partitioning, floorplanning, placement, global routing, detailed routing and layout verification. Some of the chapters are review articles, giving the state-of-the-art of the problems related to timing driven placement, global and detailed routing, and circuit partitioning. The rest of the book contains research articles, giving recent findings of new approaches to the above-mentioned problems. They are all written by leading experts in the field. This book will serve as good references for both researchers and professionals who work in this field. Seller Inventory # 9789810214883
Quantity: 2 available