ASIC Design and Synthesis : RTL Design Using Verilog

Language: English

Published by Springer, 2021

9813346418 / 9789813346413

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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Druck auf Anfrage Neuware - Printed after ordering - This book describes simple to complex ASIC design practical scenarios using Verilog.Itbuilds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, thecontentsprovide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance.Italso covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Seller Inventory # 9789813346413

Title
ASIC Design and Synthesis : RTL Design Using Verilog
Author
Vaibbhav Taraate
Publisher
Springer
Publication year
2021
Condition
Neu
Binding
Buch
Language
English
ISBN 10
9813346418
ISBN 13
9789813346413
Item weight
642 grams
Dimensions
241x160x25 mm

AHA-BUCH GmbH

Einbeck, Germany

5-star seller

AbeBooks seller since August 14, 2006

Shipping rates from Germany to U.S.A.

Item7 to 10 business days5 to 7 business days
First itemUS$ 39.21US$ 50.41
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