ASIC Implementation of Low Power FP-AU using Reversible Logic: Floating Point (FP)-Arithmetic Units (AU)

Krishnasamy Natarajan, Vijeyakumar/ Sundaram, Kalaiselvi/ Bojan, Vinoth kumar

ISBN 10: 6139587050 / ISBN 13: 9786139587056

Published by LAP LAMBERT Academic Publishing, 2018

About this Item

52 pages. 8.66x5.91x0.12 inches. In Stock.

Seller Inventory # zk6139587050

Bibliographic Details

• Title: ASIC Implementation of Low Power FP-AU using Reversible Logic: Floating Point (FP)-Arithmetic Units (AU)
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2018
• Language: English
• ISBN 10: 6139587050
• ISBN 13: 9786139587056
• Binding: Paperback
• Condition: Brand New
• Weight: 0.13 kilograms

About this title

Synopsis

This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.