ASIC Implementation of Low Power FP-AU using Reversible Logic | Floating Point (FP)-Arithmetic Units (AU)

Vijeyakumar Krishnasamy Natarajan (u. a.)

ISBN 10: 6139587050 / ISBN 13: 9786139587056

Published by LAP LAMBERT Academic Publishing, 2018

About this Item

ASIC Implementation of Low Power FP-AU using Reversible Logic | Floating Point (FP)-Arithmetic Units (AU) | Vijeyakumar Krishnasamy Natarajan (u. a.) | Taschenbuch | 52 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139587056 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 113655891

Bibliographic Details

• Title: ASIC Implementation of Low Power FP-AU using Reversible Logic | Floating Point (FP)-Arithmetic Units (AU)
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2018
• Language: English
• ISBN 10: 6139587050
• ISBN 13: 9786139587056
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 4D millimeters 220 millimeters width by 150 millimeters height by 4 millimeters depth
• Weight: 96 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.