Explore how caches shape performance in highly parallel systems and how to optimize them for speed. This book analyzes cache memories in parallel processors and the effects of policies, line sizes, and interleaving on overall performance. It blends theory and simulation to show how a well-chosen cache design can reduce memory bottlenecks in multi‑PE environments. The material is geared toward engineers and students who want practical guidance grounded in analytical and experimental results.
In a methodical, accessible style, it covers how caches operate, how data is mapped and updated, and how private and shared caches interact with central memory. You’ll find concrete discussion of cache organization for multiprocessors, performance models, and the tradeoffs involved in different design choices. The text also explains how network timing and memory interleaving influence cache effectiveness in parallel systems.
- How cache operation and mapping determine data residency and access speed
- How line size, interleaving granularity, and update policies affect traffic and latency
- How private versus shared caches behave in multiprocessor environments
- Practical guidance from analytic models and simulations for real systems
Ideal for readers of computer architecture and parallel processing who want to understand cache design in multicore and multiprocessor setups.
McAuliffe has had a long career in New York government and politics, and worked behind the scenes at City Hall as a speechwriter and press aide under New York's last three Mayors.