Automatic Layout Modification: Including Design Reuse of the Alpha CPU in 0.13 Micron Soi Technology

Michael Reinhardt

ISBN 10: 1402070918 / ISBN 13: 9781402070914

Published by Springer US, 2002

About this Item

This volume is a welcome effort towards improving some of the practices in chip design today. The authors provide a comprehensive reference work on Automatic Layout Modification which will be valuable to VLSI courses at universities, and to CAD and circu.

Seller Inventory # 458476135

Bibliographic Details

• Title: Automatic Layout Modification: Including Design Reuse of the Alpha CPU in 0.13 Micron Soi Technology
• Publisher: Springer US
• Publication Date: 2002
• Language: English
• ISBN 10: 1402070918
• ISBN 13: 9781402070914
• Binding: Gebunden
• Condition: New

About this title

Synopsis

Design reuse techniques have become the subject of books, conferences, and podium discussions over the last few years. However, most discussions focus on higher-level abstraction like RTL descriptions, which can be synthesized. Design reuse is often seen as an add-on to normal design activity, or a special design task that is not an integrated part of the existing design flow. This may all be true for the ASIC world, but not for high-speed, high-performance microprocessors.

In the field of high-speed microprocessors, design reuse is an integrated part of the design flow. The method of choice in this demanding field was, and is always, physical design reuse at the layout level. In the past, the practical implementations of this method were linear shrinks and the lambda approach. With the scaling of process technology down to 0.18 micron and below, this approach lost steam and became inefficient. The only viable solution is a method, which is now called Automatic Layout Modification (ALM). It combines compaction, mask manipulation, and correction with powerful capabilities.

Automatic Layout Modification, Including design reuse of the Alpha CPU in 0.13 micron SOI technology is a welcome effort to improving some of the practices in chip design today.