A Bit-Serial Implementation of the AES Encryption Algorithm : Implementation and Space Optimization of the Advanced Encryption Standard for a Bit-Serial Fully Pipelined Architecture

Raphael Weber

ISBN 10: 3639327136 / ISBN 13: 9783639327137

Published by VDM Verlag Dr. Müller, 2011

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization.

Seller Inventory # 9783639327137

Bibliographic Details

• Title: A Bit-Serial Implementation of the AES Encryption Algorithm : Implementation and Space Optimization of the Advanced Encryption Standard for a Bit-Serial Fully Pipelined Architecture
• Publisher: VDM Verlag Dr. Müller
• Publication Date: 2011
• Language: English
• ISBN 10: 3639327136
• ISBN 13: 9783639327137
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 22W x 15H x 0.7D centimeters 22 centimeters width by 15 centimeters height by 0.7 centimeters depth
• Weight: 195 grams

About this title

Synopsis

In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization.

About the Author

Raphael Weber is a research assistant at the OFFIS institute for information technology in Oldenburg, Germany. He studied computer science with minor in mechanical engineering at the University of Paderborn where he completed his diploma degree in 2009. His research interests include new hardware/software design and optimization methods.