CMOS Analog Integrated Circuit Layout Design and Verification: Based on Cadence IC 6.1.7(Chinese Edition)

CHEN CHENG YING YE MAO FAN JUN WANG XING HUA

Language: English

ISBN 10: 7111800354 (ISBN 13: 9787111800354)

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Seller: liu xing, Nanjing, JS, Chinaliu xing

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Language:Chinese.Paperback. Pub Date: 2026-03 Pages: 322 Publisher: China Machine Press Analog integrated circuit layout design is a crucial step in analog integrated circuit design. involving layout design. verification. and EDA tools. This book focuses on EDA tools for analog integrated circuit layout design and verification. detailing the Cadence IC 6.1.7 layout design tool and the IEMen EDA Calibre layout verification tool. It then discusses the basic syntax of Calibre DRC and LV rules. d.

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Bibliographic details

Title
CMOS Analog Integrated Circuit Layout Design and Verification: Based on Cadence IC 6.1.7(Chinese Edition)
Author
CHEN CHENG YING YE MAO FAN JUN WANG XING HUA
Condition
New
Binding
paperback
Language
English

liu xing

Nanjing, JS, China

5-star seller

AbeBooks seller since April 7, 2009

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