CMOS Circuit Design, Layout, and Simulation, Second Edition

R. Jacob Baker

ISBN 10: 047170055X / ISBN 13: 9780471700555

Published by Wiley-IEEE Press, 2004

About this Item

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Bibliographic Details

• Title: CMOS Circuit Design, Layout, and Simulation, Second Edition
• Publisher: Wiley-IEEE Press
• Publication Date: 2004
• Language: English
• ISBN 10: 047170055X
• ISBN 13: 9780471700555
• Binding: Hardcover
• Edition: 2nd Edition
• Condition: Good

About this title

Synopsis

2007 Winner of the Frederick Emmons Terman Award

CMOS: Circuit Design, Layout, and Simulation, Second Edition covers the practical design of both analog and digital integrated circuits, offering a vital contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more. This edition takes a two-path approach to the topics; design techniques are developed for both long- and short-channel CMOS technologies and then compared. The results are multidimensional explanations that allow readers deep insight into the design process.

Features include:

• Integrated-circuit layout software for Windows designed by David Boyce
• Updated materials to reflect CMOS technology's movement into nanometer sizes
• Discussions on phase- and delay-locked loops, mixed-signal circuits, data converters, and circuit noise
• More than 1,000 figures, 200 examples, and over 500 end-of-chapter problems
• In-depth coverage of both analog and digital circuit-level design techniques
• Real-world process parameters and design rules
• Associated Web site (cmosedu.com) provides examples, solutions, and SPICE simulation netlists

An Instructor's Manual presenting detailed solutions to all the problems in the book is available upon request from the Wiley Makerting Department.

About the Author

R. JACOB (JAKE) BAKER is a professor of electrical engineering at Boise State University. He teaches several courses on CMOS analog and digital circuit design and has consulted internationally in these areas. Jake holds over seventy-five granted or pending patents in integrated circuit design.