This work proposes a new EEG detection system based on a CMOS lock-in amplifier with programmable gain. The proposed lock-in amplifier consists of five stages: the first and fourth stages are 4-quadrant multipliers with a gain of 8 dB, the second stage is made of two cascaded programmable instrumentation amplifiers (IA), while the third stage is a band-pass filter (BPF) centered at 1 kHz with a gain of 7 dB, and the last stage is a low pass filter (LPF) with a gain of 30 dB and a bandwidth of 150 Hz. A basic building block is the digitally programmable balanced output operational transconductance amplifier (DPOTA), which is used in this work to realize the filters and the IA using 0.25-�m CMOS technology. The proposed lock-in amplifier is characterized by a wide programmable gain ranging from 48dB to 92dB, low power consumption of 71 �W at the maximum gain setting, and low input referred noise of 383nV/√Hz @ 20Hz. PVT and Monte Carlo simulations are also carried out to show the robustness of the proposed lock-in amplifier as a good candidate for EEG detection systems.

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