CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

The intention of this book is to address a number of timely, performance-critical issues within the field of short-distance optical communications, from a circuit designer’s perspective. It discusses the major trade-offs the designer has to deal with in the development of monolithically integrated receivers in CMOS technologies. As such, it is based on Dr. Muller’s doctoral dissertation entitled “A Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications”, subm- ted to the School of Engineering of the École Polytechnique Fédérale de Lausanne (EPFL) in May 2006. The dissertation material has been enhanced by the presentation of a number of alternative design approaches and circuit topologies, providing exhaustive coverage of the state of the art in optical sho- distance receiver circuit design. The need for a new processor input/output (I/O) interface paradigm is dictated by ongoing te- nology scaling and the advent of multi-core systems. Indeed, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput, whereas the available bandwidth of the I/O interfaces is subject to much slower growth. Moving beyond - coming serial links to an optical data link paradigm for very short-distance (board-to-board and chip-- chip communications allows for considerable I/O interface bandwidth enhancement. Fully integrated silicon CMOS receivers are considered to be the technology of choice to lead this solution to economic success, because monolithic integration results in lower volume-manufacturing cost, improved yield and reduced assembly and test expenses.

While the throughput of microprocessor systems tends to increase as a result of ongoing technology scaling and the advent of multi-core systems, the off-chip I/O communication bandwidth emerges as one of the potential bottlenecks that limit overall performance. In order to alleviate the communication speed constraints, optical data communication interfaces move ever closer to the processor core. It is widely expected that future generation digital systems will increasingly rely on chip-to-chip and board-to-board optical data communications for higher bandwidth and better noise immunity.

This book focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits.

CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications is required reading for practicing engineers and researchers in the field of short-distance optical communications and optical CMOS receiver design.