CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies | Process-Aware SRAM Design and Test

Manoj Sachdev (u. a.)

ISBN 10: 904817855X / ISBN 13: 9789048178551

Published by Springer, 2010

About this Item

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies | Process-Aware SRAM Design and Test | Manoj Sachdev (u. a.) | Taschenbuch | xvi | Englisch | 2010 | Springer | EAN 9789048178551 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Seller Inventory # 107142378

Bibliographic Details

• Title: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies | Process-Aware SRAM Design and Test
• Publisher: Springer
• Publication Date: 2010
• Language: English
• ISBN 10: 904817855X
• ISBN 13: 9789048178551
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 12D millimeters 235 millimeters width by 155 millimeters height by 12 millimeters depth
• Weight: 330 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

About the Author

Prof. Sachdev has authored several successful books with Springer