Cmos design of tree multiplier using low power vlsi and full adder

A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.In case of CMOS, addition of a single input increases the device count by 2 and thus increases the propagation delay. New logic styles were developed to minimize the propagation delay and chip area.

Sneha DravyekarMtech in VLSI at RTMNUAssistant Professor at Om Polytechnic,UmrerIndia