The book provides a detailed analysis of issues related to sub-threshold interconnect performance from the perspective of analytical approach and design techniques. Particular emphasis is laid on the performance analysis of coupling noise and variability issues in sub-threshold domain to develop efficient compact models. The proposed analytical approach gives physical insight of the parameters affecting the transient behavior of coupled interconnects. Remedial design techniques are also suggested to mitigate the effect of coupling noise. The effects of wire width, spacing between the wires, wire length are thoroughly investigated. In addition, the effect of parameters like driver strength on peak coupling noise has also been analyzed. Process, voltage and temperature variations are prominent factors affecting sub-threshold design and have also been investigated. The process variability analysis has been carried out using parametric analysis, process corner analysis and Monte Carlo technique. The book also provides a qualitative summary of the work reported in the literature by various researchers in the design of digital sub-threshold circuits. This book should be of interest for researchers and graduate students with deeper insights into sub-threshold interconnect models in particular. In this sense, this book will best fit as a text book and/or a reference book for students who are initiated in the area of research and advanced courses in nanotechnology, interconnect design and modeling.
Dr. Rohit Dhiman received his B.Tech. Degree in Electronics & Communication Engineering from H.P.U. Shimla, India in 2007. He did his M.Tech. in VLSI Design Automation & Techniques, from National Institute of Technology (NIT) Hamirpur, India in 2009. He was awarded his Ph.D. Degree from NIT Hamirpur in 2014. He has also worked as Post-Doctoral Researcher at Indian Institute of Technology (IIT) Ropar, India. Presently Dr. Rohit Dhiman has been working as an Assistant Professor at NIT Hamirpur. He has over 20 research papers in international journals of repute and conferences to his credit. His research interest is in device and circuit modeling for low power VLSI design.
Dr. Rajeevan Chandel received her B.E. Degree in E&CE from Thapar Institute of Engg. & Technology, Patiala, India in 1990. She is a double gold medalist of Himachal Pradesh University, Shimla in Pre-Univ and Pre-Engg. She did her M.Tech. in Integrated Electronics and Circuits, from IIT Delhi in 1997. She was awarded Ph.D. Degree from IIT Roorkee, India in 2005. Dr. Chandel joined Dept. of E&CE, NIT, Hamirpur, HP as Lecturer in 1990, where presently she is working as Professor & Head. She has over 40 research papers in international journals of repute and over 90 in conferences. Her research interest is in electronics circuit modeling and low power VLSI design. She is a life member of IETE (I) and ISTE (I) and member of VSI.
