Cost-effective Methods for High-speed Nanometer CMOS VLSI Design | Interconnect and Circuits. 2nd Edition

Charbel Akl

ISBN 10: 6208480620 / ISBN 13: 9786208480622

Published by LAP LAMBERT Academic Publishing, 2025

About this Item

Cost-effective Methods for High-speed Nanometer CMOS VLSI Design | Interconnect and Circuits. 2nd Edition | Charbel Akl | Taschenbuch | Englisch | 2025 | LAP LAMBERT Academic Publishing | EAN 9786208480622 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.

Seller Inventory # 133900990

Bibliographic Details

• Title: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design | Interconnect and Circuits. 2nd Edition
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2025
• Language: English
• ISBN 10: 6208480620
• ISBN 13: 9786208480622
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 8D millimeters 220 millimeters width by 150 millimeters height by 8 millimeters depth
• Weight: 215 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

The semiconductor industry has been following Moore’s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.