DIGITAL CORE OUTPUT TEST DATA COMPRESSION ARCHITECTURE : Model, Implementation, and Analysis

Language: English

Published by VDM Verlag Dr. Müller, 2009

363919098X / 9783639190984

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - With the unprecedented growth of the electronics industry, the integration densities besides system complexities continued to increase, and hence, the need for better and more effective methods of testing to assure reliable operations of chips, which is the mainstay of today s many sophisticated devices and products, was intensely felt. Generally, the cost of testing chips is prohibitive, accounting for 35% to 55% of their total manufacturing expense. Furthermore, testing an integrated circuit is also time- consuming, taking up to about one half of the total design-cycle time. On the other hand, the amount of time available for manufacturing, testing, and marketing a product is constantly on the decline. Moreover, as a result of diminishing trade barriers and global competition, customers now demand products of superior quality at lower price. However, to achieve this better quality at relatively low cost, evidently, the testing strategies have to be improved. This book is a comprehensive guide to new chip testing and built-in self-test techniques that will allow students, researchers, and chip designers to master chip design for test architectures, for diagnosis of digital cores.

Seller Inventory # 9783639190984

Title
DIGITAL CORE OUTPUT TEST DATA COMPRESSION ARCHITECTURE : Model, Implementation, and Analysis
Author
M. H. Assaf
Publisher
VDM Verlag Dr. Müller
Publication year
2009
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
363919098X
ISBN 13
9783639190984
Item weight
380 grams
Dimensions
220x176x33 mm

AHA-BUCH GmbH

Einbeck, Germany

5-star seller

AbeBooks seller since August 14, 2006

Shipping rates from Germany to U.S.A.

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