DRAM Circuit Design: A Tutorial (IEEE Press Series on Microelectronic Systems)

More dynamic random access memory (DRAM) circuits are manufactured than any other integrated circuit (IC) in production today, with annual sales in excess of US$25 billion. In the last two decades, most DRAM literature focused on the user rather than the chip designer. This comprehensive reference makes DRAM IC design accessible to both novice and practicing engineers, with a wealth of information available in one volume.

DRAM chips contain both analog and digital circuits, requiring a variety of skills and techniques to accomplish a superior design. This easy-to-read tutorial covers transistor-level design of DRAM building blocks, including the array and architecture, voltage regulators and pumps, and peripheral circuits. DRAM Circuit Design will help the IC designer prepare for the future, in which DRAM will be embedded in logic devices for complete systems on a chip.

Topics covered include:

• DRAM array
• peripheral circuitry
• global circuitry and considerations
• voltage converters
• synchronization in DRAMS.

DRAM Circuit Design is an invaluable introduction for students, academics, and practitioners with a background in electrical and computer engineering. Applications engineers and practicing IC designers will develop a better understanding of the important facets of DRAM device structure across the board.

About the Authors...
Brent Keeth began his electrical engineering career designing radar subsystems for military applications and hybrid integrated circuits for avionics control systems. He went on to design baseband scrambling and descrambling equipment for the CATV industry and professional production and post-production video equipment for the broadcast television industry. Mr. Keeth, a principal fellow at Micron Technology, Inc., has engaged in the R&D of generations of CMOS DRAMs and currently performs extensive research in high-speed bus protocols and open standard memory design. He has served on technical program committees for both the IEEE International Solid-State Circuits Conference and the Symposium on VLSI Circuits. In addition, Mr. Keeth has reviewed numerous papers for the Journal of Solid-State Circuits. He holds over 60 U.S. and foreign patents.
R. Jacob Baker is an associate professor of electrical engineering at Boise State University and a senior design engineer at Micron Technology, Inc. At Boise State, Dr. Baker teaches courses and conducts research in CMOS analog and digital integrated circuit design, while at Micron Technology he designs circuits for emerging memory technologies and DRAM interfaces. He is a coauthor of the popular textbook CMOS: Circuit Design, Layout, and Simulation (IEEE Press, 1998). Dr. Baker holds 12 patents.