Delay Uncertainty in High Performance Clock Distribution Networks

Language: English

Published by LAP LAMBERT Academic Publishing Sep 2010, 2010

3838327152 / 9783838327150

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This item is printed on demand - Print on Demand Titel. Neuware -The continuous quest for higher circuit performance has pushed clock frequencies deep into the gigahertz frequencies range, reducing the period of the clock signal well below a nanosecond. The resulting constraints demonstrate the requirement for tight timing control of the arrival times of the clock signal at the many clocked elements throughout an integrated circuit. In this book, a design methodology for enhancing the tolerance of a circuit to the uncertainty of the clock signal delay is presented. This methodology either relaxes the timing constraints at the most critical data paths, or reduces the delay uncertainty among the clock signals that synchronize these paths. Power tradeoffs of the proposed design techniques are investigated and physical layout information is incorporated to synthesize the clock tree layout based on a set of benchmark circuits. This book provides the reader with information on those effects that introduce delay uncertainty and with the tools to successfully design high performance synchronous circuits. The original research presented in this book has been awarded with the Outstanding Dissertation Award by the European Design Automation Association.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 168 pp. Englisch.

Seller Inventory # 9783838327150

Title
Delay Uncertainty in High Performance Clock Distribution Networks
Author
Dimitrios Velenis
Publisher
LAP LAMBERT Academic Publishing Sep 2010
Publication year
2010
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3838327152
ISBN 13
9783838327150
Item weight
268 grams
Dimensions
220x150x11 mm

buchversandmimpf2000

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