Design, Analysis and Test of Logic Circuits Under Uncertainty (Lecture Notes in Electrical Engineering, 115)

Krishnaswamy, Smita; Markov, Igor L.; Hayes, John P.

ISBN 10: 9048196434 / ISBN 13: 9789048196432

Published by Springer, 2012

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Bibliographic Details

• Title: Design, Analysis and Test of Logic Circuits Under Uncertainty (Lecture Notes in Electrical Engineering, 115)
• Publisher: Springer
• Publication Date: 2012
• Language: English
• ISBN 10: 9048196434
• ISBN 13: 9789048196432
• Binding: Hardcover
• Condition: New

About this title

Synopsis

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

From the Back Cover

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for:

• Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;

• Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;

• Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;

• Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.