Design, Analysis and Test of Logic Circuits under Uncertainty (Lecture Notes in Electrical Engineering)
Language: English
Published by Springer, 2012
- Hardcover
- New

Seller: Revaluation Books, Exeter, United KingdomRevaluation Books
AbeBooks seller since January 6, 2003
Condition: New
US$ 176.02
Quantity: 2 available
Add to basketItem description from seller
2013 edition. 134 pages. 9.25x6.25x0.50 inches. In Stock.
Seller Inventory # x-9048196434
- Title
- Design, Analysis and Test of Logic Circuits under Uncertainty (Lecture Notes in Electrical Engineering)
- Author
- Smita Krishnaswamy/ Igor L. Markov/ John Hayes
- Publisher
- Springer
- Publication year
- 2012
- Condition
- Brand New
- Binding
- Hardcover
- Language
- English
- ISBN 10
- 9048196434
- ISBN 13
- 9789048196432
- Item weight
- 0.36 kilograms
"Synopsis" may belong to another edition of this title.
From the Back Cover
Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for:
• Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;
• Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;
• Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;
• Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.
"About the title" may belong to another edition of this title.
Revaluation Books
Exeter, United Kingdom
AbeBooks seller since January 6, 2003
Shipping rates from United Kingdom to U.S.A.
| Item | 7 to 14 business days | 2 to 3 business days |
|---|---|---|
| First item | US$ 13.27 | US$ 39.80 |
Payment methods
Seller's business information
Edward Bowditch Ltd
Exstowe, Exton
Exeter, United Kingdom EX3 0PP
Terms of sale
Legal entity name: Edward Bowditch Ltd
Legal entity form: Limited company
Business correspondence address: Exstowe, Exton, Exeter, EX3 0PP
Company registration number: 04916632
VAT registration: GB834241546
Authorised representative: Mr. E. Bowditch
Shipping terms
Orders usually dispatched within two working days. Please note that at this time all domestic United Kingdom orders are sent by trackable UPS courier, we choose not to offer a lower cost alternative.