Design of Cost-Efficient Interconnect Processing Units

Pieralisi Lorenzo Maruccia Giuseppe Locatelli Riccardo Grammatikakis Miltos D. Coppola Marcello

ISBN 10: 1420044710 / ISBN 13: 9781420044713

Published by Taylor & Francis Group, 2008

About this Item

PRINT ON DEMAND pp. 288.

Seller Inventory # 18536376

Bibliographic Details

• Title: Design of Cost-Efficient Interconnect Processing Units
• Publisher: Taylor & Francis Group
• Publication Date: 2008
• Language: English
• ISBN 10: 1420044710
• ISBN 13: 9781420044713
• Binding: Hardcover
• Condition: New

About this title

Synopsis

Streamlined Design Solutions Specifically for NoC
To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.

A Balanced Analysis of NoC Architecture
As the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain:

• how the SoC and NoC technology works
• why developers designed it the way they did
• the system-level design methodology and tools used to configure the Spidergon STNoC architecture
• differences in cost structure between NoCs and system-level networks

From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.

About the Author

Marcello Coppola (STMicroelectronics, Grenoble, France) (Author) ,  Miltos D. Grammatikakis (ISD SA, Heraklion, Greece) (Author) ,  Riccardo Locatelli (STMicroelectronics, Grenoble Cedex, France) (Author) ,  Giuseppe Maruccia (STMicroelectronics, Grenoble, France) (Author) ,  Lorenzo Pieralisi (STMicroelectronics, Grenoble, France) (Author)