Design of DPLL using CMOS Technology

Dandare, Shankar N./ Deshmukh, Ankita

ISBN 10: 6134978159 / ISBN 13: 9786134978156

Published by LAP LAMBERT Academic Publishing, 2018

About this Item

72 pages. 8.66x5.91x0.17 inches. In Stock.

Seller Inventory # zk6134978159

Bibliographic Details

• Title: Design of DPLL using CMOS Technology
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2018
• Language: English
• ISBN 10: 6134978159
• ISBN 13: 9786134978156
• Binding: Paperback
• Condition: Brand New
• Weight: 0.15 kilograms

About this title

Synopsis

PLLs work by continuously adjusting a voltage or current-driven oscillator to match (lock onto) the phase and frequency of an input signal. A circuit called a phase comparator causes the VCO to seek and lock onto the desired frequency, which is set via a Voltage Controlled Oscillator. When the VCO frequency differs from the reference frequency, the phase comparator produces an error voltage. Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This book introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected.

About the Author

Mr. Shankar N. Dandare( M.Sc., M.E., Ph. D. ) is working as a Professor in Electronics Engineering Department, Babasaheb Naik College of Engineering, Pusad, India. He is a member of many professional bodies like ISTE, AMIE, and IETE. He has teaching experience of 34 years in Engineering UG and PG level and Main author of three engineering Books.