Design of a Data Analyser for Ethernet Packets Using VHDL : Analysis and Representation of Ethernet Communication Protocol Using Finite State Machines with VHDL Programming

Mahendra Gooroochurn

ISBN 10: 3659826944 / ISBN 13: 9783659826948

Published by LAP LAMBERT Academic Publishing, 2016

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents an in-depth analysis of the steps involved in communicating using the Ethernet protocol with the aim to design a data analyser to receive and send Ethernet packets. The various steps are represented using Finite State Machines, which are subsequently coded using VHDL programming language, and simulated. The use of VHDL programming language is a very efficient way to model digital circuit operations, and subsequently to generate hardware implementation of the desired digital processes, typically using FGPAs. It is for this reason that VHDL has become a core development tool for the digital electronics industry. The approach adopted in this work is modelling using Finite State Machines, VHDL coding and simulation, followed by testing the various structural constructs using a suitable testbench data. Being data intensive, a testbench simulation provides a useful basis to ascertain the correctness of the various elements developed when they are inter-connected. A similar approach can be used to model digital processes in a systematic and structured manner, especially for data intensive ones.

Seller Inventory # 9783659826948

Bibliographic Details

• Title: Design of a Data Analyser for Ethernet Packets Using VHDL : Analysis and Representation of Ethernet Communication Protocol Using Finite State Machines with VHDL Programming
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2016
• Language: English
• ISBN 10: 3659826944
• ISBN 13: 9783659826948
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 7D millimeters 220 millimeters width by 150 millimeters height by 7 millimeters depth
• Weight: 161 grams

About this title

Synopsis

This book presents an in-depth analysis of the steps involved in communicating using the Ethernet protocol with the aim to design a data analyser to receive and send Ethernet packets. The various steps are represented using Finite State Machines, which are subsequently coded using VHDL programming language, and simulated. The use of VHDL programming language is a very efficient way to model digital circuit operations, and subsequently to generate hardware implementation of the desired digital processes, typically using FGPAs. It is for this reason that VHDL has become a core development tool for the digital electronics industry. The approach adopted in this work is modelling using Finite State Machines, VHDL coding and simulation, followed by testing the various structural constructs using a suitable testbench data. Being data intensive, a testbench simulation provides a useful basis to ascertain the correctness of the various elements developed when they are inter-connected. A similar approach can be used to model digital processes in a systematic and structured manner, especially for data intensive ones.

About the Author

Mahendra Gooroochurn holds a doctorate in the field of Mechatronics in Medicine, and is an accredited professional in green buildings. He has taught modules in CAE, Automotive Electronics and Mechanical Systems and Control Systems. His research is in design of sustainable devices for low and renewable energy use, automation and pattern recognition.