Design and Implementation of Floating Point Vedic Multiplier in VHDL

Language: English

Published by LAP Lambert Academic Publishing Feb 2018, 2018

6137382273 / 9786137382271

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Multiplication is important operation in most of the signal processing applications.Hence,multiplier is the crucial part of signal processing applications like FIR filter,IIR filter,FFT,DFT,DCT etc.So,there is always need of a multiplier which is high speed,which consumes less area and low power.Hence performance of multiplier has direct effect on the final applications in which multipliers are used. In this book, we have tried to design optimized Vedic multiplier in HDL which can give good delay and area performance.As FIR,IIR filter have their coefficient in fraction,we have designed the multiplier in single precision floating point format. Hence,accuracy and range of multiplication coefficient is more. The Vedic multiplier is further used in FIR filer,IIR filter and Haar Wavelet transform as a basic building block.Also,it is compared with FIR filter,IIR filter and Haar Wavelet transform using other multipliers, such as Shift and Add multiplier,Array multiplier,and Wallace multiplier based on delay and area performance. 68 pp. Englisch.

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Title
Design and Implementation of Floating Point Vedic Multiplier in VHDL
Author
Kishor Upla
Publisher
LAP Lambert Academic Publishing Feb 2018
Publication year
2018
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6137382273
ISBN 13
9786137382271
Item weight
119 grams
Dimensions
220x150x5 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany