Design & Implementation of Programmable CRC Computation using FPGA

Language: English

Published by LAP LAMBERT Academic Publishing Aug 2014, 2014

3659162604 / 9783659162602

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Good error control performance requires the scheme to be selected based on the characteristics of the communication channel. Consequently, error-detecting and correcting codes can be generally distinguished between random-error-detecting/correcting and burst-error-detecting/correcting. Cyclic codes have favorable properties in that they are well suited for detecting burst errors. The cyclic redundancy check (CRC) is an error detection technique that is widely utilized in digital data communication and other fields such as data storage, data compression, etc. The work presented in describes the FPGA implementation of a CRC Decoder that has the advantages of correcting more than one bit error. Since we are introducing the hardware implementation of CRC with error correction, our main concern is about the design of the CRC decoder with error correcting capabilities. Such an optimized circuit represents an attractive hard macro for environments requiring low cost hardware flexibility, and in emerging areas such as ISCSI-based SANs, where the flexibility to adopt emerging protocols offers a key advantage to vendors. 104 pp. Englisch.

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Title
Design & Implementation of Programmable CRC Computation using FPGA
Author
Rameshwar Murade
Publisher
LAP LAMBERT Academic Publishing Aug 2014
Publication year
2014
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659162604
ISBN 13
9783659162602
Item weight
173 grams
Dimensions
220x150x7 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany