Design & Implementation of Programmable CRC Computation using FPGA

Murade, Rameshwar; Ingale, Pavan; Kale, Rahul

ISBN 10: 3659162604 / ISBN 13: 9783659162602

Published by VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2014

About this Item

Print on Demand pp. 104 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Seller Inventory # 353484991

Bibliographic Details

• Title: Design & Implementation of Programmable CRC Computation using FPGA
• Publisher: VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG
• Publication Date: 2014
• Language: English
• ISBN 10: 3659162604
• ISBN 13: 9783659162602
• Binding: Soft cover
• Condition: New

About this title

Synopsis

Good error control performance requires the scheme to be selected based on the characteristics of the communication channel. Consequently, error-detecting and correcting codes can be generally distinguished between random-error-detecting/correcting and burst-error-detecting/correcting. Cyclic codes have favorable properties in that they are well suited for detecting burst errors. The cyclic redundancy check (CRC) is an error detection technique that is widely utilized in digital data communication and other fields such as data storage, data compression, etc. The work presented in describes the FPGA implementation of a CRC Decoder that has the advantages of correcting more than one bit error. Since we are introducing the hardware implementation of CRC with error correction, our main concern is about the design of the CRC decoder with error correcting capabilities. Such an optimized circuit represents an attractive hard macro for environments requiring low cost hardware flexibility, and in emerging areas such as ISCSI-based SANs, where the flexibility to adopt emerging protocols offers a key advantage to vendors.

About the Author

M.Tech (ECE) from JNTU , Hyderabad.Lecturer in E&TC dept., SVERIs COE (POLY) Pandharpur, Pandharpur.