Design a Reversible Fault Tolerant Programmable Array Logic | An Efficient Approach

Solaiman Mia

ISBN 10: 365987552X / ISBN 13: 9783659875526

Published by LAP LAMBERT Academic Publishing, 2016

About this Item

Design a Reversible Fault Tolerant Programmable Array Logic | An Efficient Approach | Solaiman Mia | Taschenbuch | 56 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659875526 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 103800139

Bibliographic Details

• Title: Design a Reversible Fault Tolerant Programmable Array Logic | An Efficient Approach
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2016
• Language: English
• ISBN 10: 365987552X
• ISBN 13: 9783659875526
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 4D millimeters 220 millimeters width by 150 millimeters height by 4 millimeters depth
• Weight: 102 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line pairs. In this thesis, we have proposed a structure which constructs Reversible Programmable Array Logic (RPAL).An algorithm has been proposed to reduce total number of gates, garbage outputs in the AND plane of a RPAL. We compare the existing AND plane with the proposed one using benchmark functions. We make the RPLA as fault tolerant. Our proposed design can realize ESOP (Exclusive Sum-of-Products) operations in terms of multi-output functions by using minimum number of gates, garbage outputs and quantum cost. In our design, we have used fault tolerant FRG (Fredkin Gate) and F2G (Feynman Double Gate) for making our RPAL Fault Tolerant. We have also proposed a non fault tolerant design for RPAL with the minimum number of gates, garbage outputs and quantum cost.

About the Author

Md. Solaiman Mia received the B.Sc.(Hons.) and M.S. in the Dept. of Computer Science & Engineering from University of Dhaka, Bangladesh. He is currently working as a Lecturer with the Dept. of Computer Science & Engineering, Hamdard University Bangladesh. His research interests include Reversible Logic Synthesis, Quantum Computing etc.