Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Brandon Noia

ISBN 10: 3319345346 / ISBN 13: 9783319345345

Published by Springer, 2016

About this Item

reprint edition. 264 pages. 9.25x6.10x0.62 inches. In Stock.

Seller Inventory # 3319345346

Bibliographic Details

• Title: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
• Publisher: Springer
• Publication Date: 2016
• Language: English
• ISBN 10: 3319345346
• ISBN 13: 9783319345345
• Binding: Paperback
• Condition: Brand New
• Weight: 4.53 kilograms

About this title

Synopsis

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

About the Author

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.