The Designer's Guide to VHDL

The Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from system level down to gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
The book is organized so that it can either be read cover to cover for a comprehensive tutorial or be kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. In addition, each chapter is followed by a set of rated exercises.

Peter J. Ashenden is a professor of computer science and computer engineering at the University of Adelaide, Australia. He actively researches design methods and computer aided design tools for VHDL, and he is a participant in the IEEE working groups that develop VHDL and related standards. He is the author of The VHDL Cookbook and The Designer's Guide to VHDL (Morgan Kaufmann Publishers, 1995).