Designing Digital Computer Systems with Verilog (Hardcover)

David J. Lilja

ISBN 10: 052182866X / ISBN 13: 9780521828666

Published by Cambridge University Press, Cambridge, 2004

About this Item

Hardcover. This unique book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioral and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers. This is both an introduction to computer architecture and a guide to using a hardware description language (HDL) to design a simple processor. The authors demonstrate how behavioural and structural models can be developed using the popular Verilog HDL. For senior and graduate students, and practising engineers. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9780521828666

Bibliographic Details

Title: Designing Digital Computer Systems with ...

Publisher: Cambridge University Press, Cambridge

Publication Date: 2004

Binding: Hardcover

Condition: new

About this title

Synopsis:

Using Verilog, a leading commercial hardware description language, this text describes how to specify, design, and test a complete digital system. After a brief introduction to the Verilog language, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. The remainder of the book demonstrates how both behavioral and structural models can be developed and intermingled in Verilog.

About the Authors:

DAVID LILJA received his PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign. He is currently a Professor of Electrical and Computer Engineering , and a Fellow of the Minnesota Supercomputing Institute, at the University of Minnesota in Minneapolis. He also serves as a member of the graduate faculties in Computer Science and Scientific Computation, and was the founding Director of Graduate Studies for Computer Engineering. He has served on the program committees of numerous conferences and as associate editor for IEEE Transactions on Computers. David is a Senior member of the IEEE and a member of the ACM.

SACHIN SAPATNEKAR received his PhD from the University of Illinois at Urbana-Champaign. Currently, he is the Robert and Marjorie Henle Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, and serves on the graduate faculty in Computer Science and Engineering. He has served as Associate Editor for several IEEE journals, a distinguished visitor for the IEEE Computer Society and a distinguished lecturer for the IEEE Circuits and Systems Society. He is a recipient of the NSF Career Award and the SRC Technical Excellence Award. He is a Fellow of the IEEE and a member of the ACM.