Device Design in Sub-Threshold Region for Ultra Low Power Applications

The decreasing feature size of CMOS circuits and corresponding increase in chip density and operating frequency is the compelling concern of power consumption in VLSI design. The increasing prominence of portable systems and need to limit power consumption has led to rapid and innovative developments in low power VLSI design during recent years. In this book, Low power VLSI device design is considered as the main area of research. Interconnects, gates, flip-flops, and latches are the basic building blocks of any complex VLSI system. Operability of the designs is tested for the range of frequencies, supply voltages, and temperatures. Finally, the best designs are proposed.

Received B.E. degree in E&C from M.M.M. Engineering College, Gorakhpur and completed M.Tech. in VLSI Design from FET-MITS, Sikar. He has completed his Ph.D. in Low power VLSI design field. He published research papers in reputed International/National journals and conferences. He is also Editorial board member and reviewer of well reputed journals.