Dielectric and Work Function Engineered Doping-Less Tunnel FET

G. Lakshmi Priya

ISBN 10: 620267203X / ISBN 13: 9786202672030

Published by LAP LAMBERT Academic Publishing Aug 2020, 2020

About this Item

This item is printed on demand - it takes 3-4 days longer - Neuware -The perpetual downscaling of devices has achieved higher packaging density and faster switching performance. As the physical dimensions of FET device are scaled down consistently, many undesirable Short Channel Effects (SCEs) and subthreshold leakage current becomes more dominant and deteriorates the performance of the devices. The major driving force for the proposed book is to overcome all these above limitations with advancements in the materials science and semiconductor industry. Doping-Less Tunnel FET's (Junctionless Tunnel FET - JLTFET) have evolved as the most gratifying candidate. The absence of gradient doping concentration makes the fabrication process much simpler and offers low thermal budget. The high-K gate stack engineered device overcomes the SCEs caused by the ultrathin silicon devices. This book is designed to formulate a subthreshold model for Dual Metal Dielectric Engineered Doping-Less Tunnel FET by solving a two-dimensional Poisson's equation using Parabolic approximation method. Also, the impact of different high-K gate oxide materials with Silicon dioxide is also studied using TCAD Sentaurus device simulator. 200 pp. Englisch.

Seller Inventory # 9786202672030

Bibliographic Details

• Title: Dielectric and Work Function Engineered Doping-Less Tunnel FET
• Publisher: LAP LAMBERT Academic Publishing Aug 2020
• Publication Date: 2020
• Language: English
• ISBN 10: 620267203X
• ISBN 13: 9786202672030
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 12D millimeters 220 millimeters width by 150 millimeters height by 12 millimeters depth
• Weight: 316 grams

About this title

Synopsis

The perpetual downscaling of devices has achieved higher packaging density and faster switching performance. As the physical dimensions of FET device are scaled down consistently, many undesirable Short Channel Effects (SCEs) and subthreshold leakage current becomes more dominant and deteriorates the performance of the devices. The major driving force for the proposed book is to overcome all these above limitations with advancements in the materials science and semiconductor industry. Doping-Less Tunnel FET’s (Junctionless Tunnel FET - JLTFET) have evolved as the most gratifying candidate. The absence of gradient doping concentration makes the fabrication process much simpler and offers low thermal budget. The high-K gate stack engineered device overcomes the SCEs caused by the ultrathin silicon devices. This book is designed to formulate a subthreshold model for Dual Metal Dielectric Engineered Doping-Less Tunnel FET by solving a two-dimensional Poisson’s equation using Parabolic approximation method. Also, the impact of different high-K gate oxide materials with Silicon dioxide is also studied using TCAD Sentaurus device simulator.