Digital System Design with VHDLMark ZwolinskiElectronic systems based on digital principles are becoming ubiquitous. A good design approach to these systems is essential and a top-down methodology is favoured. Such an approach is vastly simplified by the use of computer modelling to describe the systems. VHDL is a design language which allows a designer to model the behaviour and structure of a digital circuit on a computer before implementation and to automatically synthesize the structure from a high-level description.Digital System Design with VHDL is intended both for students on Digital Design courses and practitioners who would like to integrate digital design and VHDL synthesis in the workplace.Its unique approach combines the principles of digital design with a guide to the use of VHDL. Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance.Features: ? a practical perspective is obtained by the inclusion of numerous examples? applies software engineering practices to encourage clear coding and adequate documentation of the process? demonstrates the effects of particular coding styles on synthesis and simulatio
Electronic systems based on digital principles are becoming ubiquitous. A good design approach to these systems is essential and a top-down methodology is favoured. Such an approach is vastly simplified by the use of computer modeling to describe the systems. VHDL is a formal language which allows a designer to model the behaviours and structure of a digital circuit on a computer before implementation.
Digital System Design with VHDL is intended both for students on Digital Design courses and practitioners who would like to integrate digital design and VHDL synthesis in the workplace.
Its unique approach combines the principles of digital design with a guide to the use of VHDL. Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance.
Features:
- a practical perspective is obtained by the inclusion of real-life examples
- an emphasis on software engineering practices encourages clear coding and adequate documentation of the process
- demonstrates the effects of particular coding styles on synthesis and simulation efficiency
- covers the major VHDL standards
- includes an appendix with examples in Verilog
