Digital Systems Design Using Vhdl

Roth, Charles H., Jr.; John, Lizy Kurian

ISBN 10: 0495244708 / ISBN 13: 9780495244707

Published by CL Engineering, 2007

About this Item

Unread book in perfect condition.

Seller Inventory # 4965481

Bibliographic Details

• Title: Digital Systems Design Using Vhdl
• Publisher: CL Engineering
• Publication Date: 2007
• Language: English
• ISBN 10: 0495244708
• ISBN 13: 9780495244707
• Binding: Soft cover
• Condition: As New

About this title

Synopsis

Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design, the author introduces the basics of VHDL, and then incorporates more coverage of advanced VHDL topics. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process.

Review

1. Review of Logic Design Fundamentals Combinational Logic / Boolean Algebra and Algebraic Simplification / Karnaugh Maps / Designing with NAND and NOR Gates / Hazards in Combinational Circuits / Flip-Flops and Latches / Mealy Sequential Circuit Design / Design of a Moore Sequential Circuit / Equivalent States and Reduction of State Tables / Sequential Circuit Timing / Tristate Logic and Busses 2. Introduction to VHDL Computer-Aided Design / Hardware Description Languages / VHDL Description of Combinational Circuits / VHDL Modules / Sequential Statements and VHDL Processes / Modeling Flip-Flops Using VHDL Processes / Processes Using Wait Statements / Two Types of VHDL Delays: Transport and Inertial Delays / Compilation, Simulation, and Synthesis of VHDL Code / VHDL Data Types and Operators / Simple Synthesis Examples / VHDL Models for Multiplexers / VHDL Libraries / Modeling Registers and Counters Using VHDL Processes / Behavioral and Structural VHDL / Variables, Signals, and Constants / Arrays / Loops in VHDL / Assert and Report Statements 3. Introduction to Programmable Logic Devices Brief Overview of Programmable Logic Devices / Simple Programmable Logic Devices (SPLDs) / Complex Programmable Logic Devices (CPLDs) / Field-Programmable Gate Arrays (FPGAs) 4. Design Examples BCD to 7-Segment Display Decoder / A BCD Adder / 32-Bit Adders / Traffic Light Controller / State Graphs for Control Circuits / Scoreboard and Controller / Synchronization and Debouncing / A Shift-and-Add Multiplier / Array Multiplier / A Signed Integer/Fraction Multiplier / Keypad Scanner / Binary Dividers 5. SM Charts and Microprogramming State Machine Charts / Derivation of SM Charts / realization of SM Charts / Implementation of the Dice Game / Microprogramming / Linked State Machines 6. Designing with Field Programmable Gate Arrays Implementing Functions in FPGAs / Implementing Functions Using Shannon's Decomposition / Carry Chains in FPGAs / Cascade Chains in FPGAs / Examples of Logic Blocks in Commercial FPGAs / Dedicated Memory in FPGAs / Dedicated Multipliers in FPGAs / Cost of Programmability / FPGAs and One-Hot State Assignment / FPGA Capacity: Maximum Gates Versus Usable Gates / Design Translation (Synthesis) / Mapping, Placement, and Routing 7. Floating-Point Arithmetic Representation of Floating-Point Numbers / Floating-Point Multiplication / Floating-Point Addition / Other Floating-Point Operations 8. Additional Topics in VHDL VHDL Functions / VHDL Procedures / Attributes / Creating Overloaded Operators / Multi-Valued Logic and Signal Resolution / The IEEE 9-Valued Logic System / SRAM Model Using IEEE 1164 / Model for SRAM Read/Write System / Generics / Named Association / Generate Statements / Files and TEXTIO 9. Design of a Risc Microprocessor The RISC Philosophy / The MIPS ISA / MIPS Instruction Encoding / Implementation of a MIPS Subset / VHDL Model 10. Hardware Testing and Design for Testability Testing Combinational Logic / Testing Sequential Logic / Scan Testing / Boundry Scan / Built-In Self-Test 11. Additional Design Examples Design of a Wristwatch / Memory Timing Models / A Universal Asynchronous Receiver Transmitter (UART) Appendix A VHDL Language Summary Appendix B IEEE Standard Libraries Appendix C TEXTIO Package Appendix D Projects References