Duper Scalar Processor

Intekhab Sadekin

ISBN 10: 3844329498 / ISBN 13: 9783844329490

Published by LAP LAMBERT Academic Publishing Apr 2011, 2011

About this Item

This item is printed on demand - it takes 3-4 days longer - Neuware -This paper proposes an architecture that brings in a new dimension to instruction level parallelism. The operating system in today's machines does all the decision making as to how the instructions in a task can be parallelized by deciding which task gets assigned to which core. The hardware support for exploiting instruction level parallelism is very small and has very little decision making power. Most recently dynamic scheduling of the instructions paved the pathway for major hardware changes and hence the decision making power shared. But the problem still persists. The operating has no direct help from the hardware and has to do most of the work at software level and hence the operating system has to be modified as the number of cores increase and the type of cores change. So a hardware support is a necessity in order to keep the operating system unchanged so that it doesn't have to worry about the cores. The concept that I proposed plan to release the OS designer from this burden by introducing a Hardware Virtual Processor that will appear as a single processor to the OS, but inside it will be multiple specialized cores executing instructions in parallel. 72 pp. Englisch.

Seller Inventory # 9783844329490

Bibliographic Details

• Title: Duper Scalar Processor
• Publisher: LAP LAMBERT Academic Publishing Apr 2011
• Publication Date: 2011
• Language: English
• ISBN 10: 3844329498
• ISBN 13: 9783844329490
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 125 grams

About this title

Synopsis

This paper proposes an architecture that brings in a new dimension to instruction level parallelism. The operating system in today's machines does all the decision making as to how the instructions in a task can be parallelized by deciding which task gets assigned to which core. The hardware support for exploiting instruction level parallelism is very small and has very little decision making power. Most recently dynamic scheduling of the instructions paved the pathway for major hardware changes and hence the decision making power shared. But the problem still persists. The operating has no direct help from the hardware and has to do most of the work at software level and hence the operating system has to be modified as the number of cores increase and the type of cores change. So a hardware support is a necessity in order to keep the operating system unchanged so that it doesn't have to worry about the cores. The concept that I proposed plan to release the OS designer from this burden by introducing a Hardware Virtual Processor that will appear as a single processor to the OS, but inside it will be multiple specialized cores executing instructions in parallel.

About the Author

I am an aspiring software engineer with a strong passion for research. I have always been keen on research and that is why I try to expose myself to various areas of interest whether it be computer architecture, reconfigurable computing, web application development methodologies or natural language processing. I am also a cricket fanatic.