Efficient Hardware Implementation of an Advanced Turbo Decoder | An ASIC Implementation

Naresh Kumar Venkatesh

ISBN 10: 3847308556 / ISBN 13: 9783847308553

Published by LAP Lambert Academic Publishing, 2012

About this Item

Efficient Hardware Implementation of an Advanced Turbo Decoder | An ASIC Implementation | Naresh Kumar Venkatesh | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783847308553 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 106525796

Bibliographic Details

• Title: Efficient Hardware Implementation of an Advanced Turbo Decoder | An ASIC Implementation
• Publisher: LAP Lambert Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3847308556
• ISBN 13: 9783847308553
• Binding: Taschenbuch
• Condition: Neu
• Seller catalogs:
  • Bücher

About this title

Synopsis

Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler.

About the Author

I have completed M.Sc [Engineering] VLSI System Design at M.S. Ramaiah School of Advanced Studies, Bangalore.