Energy Efficient and Fault-tolerant Computing

Jayaram Natarajan

ISBN 10: 6138916204 / ISBN 13: 9786138916208

Published by Scholars' Press Okt 2019, 2019

About this Item

Neuware -One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 136 pp. Englisch.

Seller Inventory # 9786138916208

Bibliographic Details

• Title: Energy Efficient and Fault-tolerant Computing
• Publisher: Scholars' Press Okt 2019
• Publication Date: 2019
• Language: English
• ISBN 10: 6138916204
• ISBN 13: 9786138916208
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 9D millimeters 220 millimeters width by 150 millimeters height by 9 millimeters depth
• Weight: 221 grams

About this title

Synopsis

One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.