Energy-Performance Characterization of CMOS/MTJ Hybrid Circuits: Can Magnetic Tunnel Junction (MTJ) help CMOS technology become ultra-low power

Ren, Fengbo

ISBN 10: 3659298913 / ISBN 13: 9783659298912

Published by LAP LAMBERT Academic Publishing, 2012

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Bibliographic Details

• Title: Energy-Performance Characterization of CMOS/MTJ Hybrid Circuits: Can Magnetic Tunnel Junction (MTJ) help CMOS technology become ultra-low power
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3659298913
• ISBN 13: 9783659298912
• Binding: Paperback
• Condition: Like New
• Book Type: book

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Synopsis

The explosive growth of the semiconductor industry has been driven by the rapid scaling of CMOS technology. Yet, as scaling getting closer to the physical limit, the increasing device leakage and viability greatly deteriorate the energy efficiency and stability of CMOS circuits. In order to extend the scaling and alleviate the leakage problem, various emerging electrical switches have been suggested in the ITRS roadmap. However, CMOS technology will continue to advance and lead the semiconductor industry regardless. Thus, in short term, people will keep looking for new switches that are CMOS-compatible and can supplement CMOS for ultra-low-power operations. Magnetic Tunnel Junction (MTJ) is a great candidate for these goals, as its non-volatility and CMOS-compatibility allows for realizing CMOS/MTJ hybrid circuits, where the operation states can be stored in MTJ cells in a distributed fashion and fine-grain power gating can be realized to eliminate the standby power. In this book, we discuss how such hybrid logic circuits can be realized. We also characterize their energy and performance improvements over conventional CMOS designs in both circuit and architecture level benchmarks.

About the Author

Dr. Ren received the B.Eng. degree from Zhejiang University and the M.S. and Ph.D degrees from UCLA in 2008, 2010 and 2013, respectively, all in EE. His current research interests include circuit design and design optimization for STT-RAM and efficient DSP architectures for the sparse signal processing in compressive sensing applications.