FPGA Based Network Security Architecture for High Speed Networks | Design and Implementation of efficient architectures of time critical modules in FPGA for High Speed Network Application

Sourav Mukherjee (u. a.)

ISBN 10: 3845414790 / ISBN 13: 9783845414799

Published by LAP LAMBERT Academic Publishing, 2011

About this Item

FPGA Based Network Security Architecture for High Speed Networks | Design and Implementation of efficient architectures of time critical modules in FPGA for High Speed Network Application | Sourav Mukherjee (u. a.) | Taschenbuch | 80 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783845414799 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu.

Seller Inventory # 106883567

Bibliographic Details

• Title: FPGA Based Network Security Architecture for High Speed Networks | Design and Implementation of efficient architectures of time critical modules in FPGA for High Speed Network Application
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2011
• Language: English
• ISBN 10: 3845414790
• ISBN 13: 9783845414799
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 6D millimeters 220 millimeters width by 150 millimeters height by 6 millimeters depth
• Weight: 137 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Cryptography and Network Security in high speed networks demands for specializedhardware in order to match up with the network speed. These hardwaremodules are being realized using reconfigurable FPGA technology to supportheavy computation. Our work is mainly based on designing an efficient architecturefor a cryptographic module and a network intrusion detection system for ahigh speed network. All the designs are coded using VHDL and are synthesizedusing Xilinx ISE for verifying their functionality. Virtex II pro FPGA is chosenas the target device for realization of the proposed design. The Network IntrusionDetection System (NIDS) module is designed for scanning suspicious patterns indata packets incoming to the network. Scanning a data packet against multiplepatterns in quick time is a highly computational intensive task. The design goal is to increasethe data conversion rate i.e the throughput to a substantial value so thatthe design can be used as a separate hardware module in high speed network applications.

About the Author

SOURAV MUKHERJEE received the B.Tech. degree in CSE from WBUT, Kolkata, India in 2008. He has recently completed his M.Tech. in CSE from NIT Rourkela, India in 2011. BIBHUDATTA SAHOO received the ME in CSE from NIT Rourkela, INDIA, in 1999. He is currently an assistant professor in the Dept of CSE, NIT Rourkela,India.