Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation

Lars Wehmeyer

ISBN 10: 1402048211 / ISBN 13: 9781402048210

Published by Springer Jul 2006, 2006

About this Item

Neuware - Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Seller Inventory # 9781402048210

Bibliographic Details

• Title: Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation
• Publisher: Springer Jul 2006
• Publication Date: 2006
• Language: English
• ISBN 10: 1402048211
• ISBN 13: 9781402048210
• Binding: Buch
• Condition: Neu

About this title

Synopsis

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

About the Author

Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.