FinFET Modeling for IC Simulation and Design

This book is the first to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard.

The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.

With this book you will learn:

• Why you should use FinFET
• The physics and operation of FinFET
• Details of the FinFET standard model (BSIM-CMG)
• Parameter extraction in BSIM-CMG
• FinFET circuit design and simulation

• Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CM standard model, providing an experts’ insight into the specifications of the standard
• The first book on the industry-standard FinFET model - BSIM-CMG

Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.

Darsen D. Lu was one of the key contributors of the industry standard FinFET compact model, BSIM-CMG, and thin-body SOI compact model, BSIM-IMG. He received his B.Sc. in electrical engineering in 2005, from National Tsing Hua University, Hsinchu, Taiwan, and his M.Sc. and Ph.D. in electrical engineering from the University of California, Berkeley, in 2007 and 2011 respectively. From 2011 to 2015, he has been a research scientist at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York. He is currently a Macronix Endowed Chair (Associate) Professor at National Cheng Kung University, Tainan, Taiwan. His current research focuses on the fabrication and modeling of ferroelectric memory (ferroelectric FinFET) devices, cryogenic CMOS modeling for high-performance and quantum computation, and the design of AI/neuromorphic circuits and systems.

Sriramkumar Venugopalan received his M.Sc. and Ph.D. in electrical engineering at the University of California, Berkeley and his B.Sc. from the Indian Institute of Technology (IIT), Kanpur. While pursuing his doctoral degree he contributed to research and development of multi-gate transistor compact SPICE models. He lead the industry standardization effort for BSIM-CMG model representing the BSIM Group at the Compact Model Council. He was the recipient of Outstanding Researcher Award from TSMC for his contributions to multi-gate SPICE models. He has authored and co- authored more than 30 research papers in the area of semiconductor device SPICE models and RF integrated circuit design. Dr. Venugopalan is currently leading wireless system design group at Skyworks Solutions, Inc. Prior to that he co-founded and was the CEO of RF Pixels, a 5G mmWave Radio startup which was later acquired by Skyworks. Dr. Venugopalan was also with Samsung Electronics pursuing RF integrated circuit design in advanced semiconductor technology nodes.

Sourabh Khandelwal is an Associate Professor at Macquarie University. He is the lead author of two industry standard compact models: ASM-HEMT for GaN RF and power technology, and ASM-ESD for silicon ESD applications. He has also co-authored BSIM-CMG, BSIM-IMG and BSIM6 compact models during his tenure at the BSIM group at the University of California Berkeley. Dr Khandelwal has published 3 books and over 150 research papers. He regularly serves as consultant to multi-national semiconductor companies.

Juan Pablo Duarte Sepúlveda obtained his Ph.D. at the University of California, Berkeley in 2018. He received his B.Sc. in 2010 and his M.Sc. in 2012, both in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at the Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers on nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper: Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.