Finfet/Gaa Modeling for IC Simulation and Design | Using the Bsim-Cmg Standard
Language: English
Published by Elsevier Science, 2024
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Finfet/Gaa Modeling for IC Simulation and Design | Using the Bsim-Cmg Standard | Yogesh Singh Chauhan (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2024 | Elsevier Science | EAN 9780323957298 | Verantwortliche Person für die EU: Elsevier B.V., Radarweg 29, 1043 NX AMSTERDAM, NIEDERLANDE, productsafety[at]elsevier[dot]com | Anbieter: preigu.
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- Title
- Finfet/Gaa Modeling for IC Simulation and Design | Using the Bsim-Cmg Standard
- Author
- Yogesh Singh Chauhan (u. a.)
- Publisher
- Elsevier Science
- Publication year
- 2024
- Condition
- Neu
- Binding
- Taschenbuch
- Language
- English
- ISBN 10
- 0323957293
- ISBN 13
- 9780323957298
- Edition
- 2nd Edition
- Item weight
- 682 grams
- Dimensions
- 232 x 187 x 19 mm
- Seller catalogs
- Bücher
FinFET/GAA Modeling for IC Simulation and Design: Using the BSIM-CMG Standard, Second Edition is the first to book to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, thus providing a step-by-step approach for the efficient extraction of model parameters.
With this book, users will learn Why you should use FinFET, The physics and operation of FinFET Details of the FinFET standard model (BSIM-CMG), Parameter extraction in BSIM-CMG FinFET circuit design and simulation, and more.
- Authored by the lead inventor and developer of FinFET and developers of the BSIM-CMG standard model, providing an expert’s insight into the specifications of the standard
- A new edition of the original groundbreaking book on the industry-standard FinFET model―BSIM-CMG
- Includes a new chapter providing a comprehensive introduction to GAAFET, including motivations, device concepts, structure, benefits, and the industry standard GAAFET model
- Covers the most recent developments in the BSIM-CMG model
- Presents an updated RF modeling of FinFET using the BSIM-CMG model including parameter extraction
- Includes a new chapter on cryogenic modeling
"Synopsis" may belong to another edition of this title.
About the Author
Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching – the Berkeley Distinguished Teaching Award.
Sayeef Salahuddin is the TSMC Distinguished Chair Professor at the University of California, Berkeley He received the Presidential Early Career Award for Scientists and Engineers by President Obama among several other early career awards from multiple federal agencies. He also received the IEEE Andrew S Grove Award for his pioneering work in ferroelectric negative capacitance and its incorporation into the most advanced DRAM memory and back-end capacitors. He is a Fellow of the IEEE, APS and AAAS and is the editor-in-chief of the IEEE Electron Devices Letters.
Girish Pahwa is an assistant professor at the International College of Semiconductor Technology at National Yang Ming Chiao Tung University. Girish’s research primarily focuses on the modeling, simulation, and device-circuit co-design of upcoming and emerging nanoscale technologies.
Before his current role, Girish held multiple positions in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley including assistant professional researcher, postdoctoral scholar, and research and development engineer. He also served as the inaugural executive director of the Berkeley Device Modeling Center (BDMC) and made significant contributions to the BSIM suite of compact models. His notable works include the development of industry-focused compact models for cryogenic CMOS operation, ferroelectric devices, high-voltage MOSFETs, and thin film transistors.
Girish has received several prestigious awards, including the IEEE EDS Early Career Award (2022), the Outstanding Ph.D. Thesis Award from IIT Kanpur (2020), and the Best Paper Award at the IEEE International Conference on Emerging Electronics (2016). He is an active member of the IEEE EDS Compact Modeling Committee and the IEEE EDS Electronic Materials Committee. He has served as a reviewer for several journals and conferences and has been part of the technical program committee for the IEEE Electron Devices Technology and Manufacturing (EDTM) conference.
Girish earned his Ph.D. and master’s degrees in electrical engineering from the Indian Institute of Technology (IIT) Kanpur and his bachelor’s degree in electronics and communication engineering from Delhi Technological University.
Avirup Dasgupta is a faculty member in the Dept. of Electronics and Communication Engineering at the Indian Institute of Technology Roorkee (IITR), where he leads the DiRac Lab. His work primarily involves semiconductor physics, modeling and design of semiconductor devices and EDA. Prof. Dasgupta is a co-developer of multiple industry standard models including BSIM-BULK, BSIM-IMG, BSIM-CMG, BSIM-SOI and ASM-HEMT. He also develops various compact models for different industry clients. Prof. Dasgupta is an IEEE Senior Member and the recipient of multiple awards including the IEEE EDS Early Career Award (2021). He has served as the reviewer for multiple journals and conferences and serves as a member of the IEEE EDS Compact Modeling Technical Committee, IEEE EDS Publications and Products Standing Committee and IEEE UP Section Executive Committee.
Prof. Dasgupta completed his undergraduate, graduate and doctoral work at the Indian Institute of Technology Kanpur (IITK). He worked as the manager of the Berkeley Device Modeling Center (BDMC) and as a postdoctoral scholar in the BSIM group at the Dept. of Electrical Engineering and Computer Science, University of California Berkeley, prior to joining IITR.
"About the title" may belong to another edition of this title.
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