Foreign electronic communications textbook series: Verilog HDL Advanced Digital Design (Second Edition)(Chinese Edition)

[?]Michael D.Ciletti ???,???,??,?

ISBN 10: 7121221934 ISBN 13: 9787121221934

Published by ???????, 2014

Language: Chinese

Condition: Used - Good Soft cover

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Title

Foreign electronic communications textbook series: Verilog HDL Advanced Digital Design (Second Edition)(Chinese Edition)

Publisher

???????

Publication Date

2014

Language

Chinese

ISBN 10

7121221934

ISBN 13

9787121221934

Binding

Paperback

Condition

Good

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No Jacket

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《国外电子与通信教材系列：VerilogHDL高级数字设计（第2版）》依据数字集成电路系统工程开发的要求与特点，利用VerilogHDL对数字系统进行建模、设计与验证，对ASIC/FPGA系统芯片工程设计开发的关键技术与流程进行了深入讲解，内容包括：集成电路芯片系统的建模、电路结构权衡、流水线技术、多核微处理器、功能验证、时序分析、测试平台、故障模拟、可测性设计、逻辑综合、后综合验证等集成电路系统的前后端工程设计与实现中的关键技术及设计案例。书中以大量设计实例叙述了集成电路系统工程开发须遵循的原则、基本方法、实用技术、设计经验与技巧。第1章数字设计方法概论电路设计的经典设计方法是依赖于电路原理图的人工设计方法，而现在的大规模复杂电路广泛采用基于计算机语言的现代设计方法。这种实践变革有几方面的原因，其中最重要的原因是没有任何一支设计工程师团队能够用人工方法有效、全面、正确地设计和管理含数百万门级的现代集成电路（ⅡC）。但使用硬件描述语言（HDL），工程师们能很容易地实现对大型复杂电路系统的设计和管理。即使小规模电路的设计也更多地依赖于基于语言的描述，因为工程师们必须快速设计生产出满足瞬息万变的市场需求的产品。基于语言的设计易于移植且不依赖于工艺，设计团队也可以重用或修改以前的设计，以保持与更先进工艺的一致性。随着器件物理尺寸的缩小，电路密度的提高，基于原有HDL模型进行综合生成的电路同样具有更高的性能。硬件描述语言也是将各种设计专利成果集成为知识产权核（IP）的一种方便而有效的工具和手段。通过使用这种通用设计语言的描述，电路模块可以根据需要单独或合并进行综合和测试，以缩短设计周期。有些仿真工具还支持基于多种语言的混合描述。采用HDL最显著的优点在于：基于语言描述的电路及其优化可以自动地进行综合，而不用经历人工设计方法中那些费力的步骤（如用卡诺图化简逻辑函数）。目前，基于HDL的综合方法是工业界普遍采用的主流设计方法。设计者可以通过构建一个软件原型或模型来验证其功能，然后利用综合工具自动对所设计的电路进行优化，并且可以生成针对某物理工艺技术的网表（nctlist）。HDL和综合工具的应用使得工程师们更关注有关功能的设计，而不是具体的单个晶体管或逻辑门的设计；综合得到的电路可以实现预期的功能，并满足面积和／或性能的约束要求。无论是功能模型还是行为模型的HDL模型描述，都可综合出不同的结构，并可据此快速对设计进行评估和折中。HDL可作为多种设计工具的平台，包括：设计输入、设计验证、测试向量生成、故障分析和仿真、时序分析和／或验证、综合和原理图的自动生成等任务。HDL这种宽范围的覆盖使得设计者的设计工作通过工具链路时，由于不再需要考虑设计描述在不同工具间的转换过程而大大提高了设计流程的工作效率。Veriog和VHDL两种语言受到工业界的广泛支持，这两种语言都成为了IEEE（电气和电子工程师协会）标准，并都得到ASIC（专用集成电路）和PPGA（现场可编程门阵列）相关综合工具的支持。模拟电路设计语言，如SpiceL3，，在验证电路的关键时序路径上扮演着重要角色。但由于这些模拟电路描述语言对大型设计来说需要大得惊人的计算量，而且也

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